公开(公告)号：US20240021730A1

公开(公告)日：2024-01-18

申请号：US18475441

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/42356 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/78654 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66772 ,  H01L27/092 ,  H01L21/823807 ,  H01L27/0688 ,  H01L2029/7858

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20240313097A1

公开(公告)日：2024-09-19

申请号：US18513740

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGIL YANG ,  TAEHYUN KIM ,  TAEWON HA

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a first region and a second region; an active region on the first region and a peripheral active region on the second region; a channel pattern on the active region; a peripheral channel pattern on the peripheral active region; a first gate electrode on the channel pattern; and a second gate electrode on the peripheral channel pattern. A linewidth of the second gate electrode is larger than a linewidth of the first gate electrode, and a difference in height between the first and second gate electrodes is smaller than about 10 nm, and a top surface of the second gate electrode has a doubly-concave shape.

公开(公告)号：US20200381547A1

公开(公告)日：2020-12-03

申请号：US16743206

申请日：2020-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20200343378A1

公开(公告)日：2020-10-29

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20220254781A1

公开(公告)日：2022-08-11

申请号：US17468139

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： INHYUN SONG ,  JUNGGIL YANG ,  Minju KIM

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.

公开(公告)号：US20190181257A1

公开(公告)日：2019-06-13

申请号：US16018121

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20240339451A1

公开(公告)日：2024-10-10

申请号：US18744905

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： INHYUN SONG ,  JUNGGIL YANG ,  Minju KIM

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/4908 ,  H01L21/28088 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.

公开(公告)号：US20230290881A1

公开(公告)日：2023-09-14

申请号：US18321962

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/42392 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20220093786A1

公开(公告)日：2022-03-24

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.