公开(公告)号：US12046526B2

公开(公告)日：2024-07-23

申请号：US17735471

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Jae Gwon Jang ,  Gwang Jae Jeon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/3128 ,  H01L21/565 ,  H01L24/19 ,  H01L23/293

Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

公开(公告)号：US11715645B2

公开(公告)日：2023-08-01

申请号：US17656695

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Seok Hyun Lee ,  Jae Gwon Jang ,  Gwang Jae Jeon

IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/52 ,  H01L21/565 ,  H01L23/49816 ,  H01L25/50

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US11328970B2

公开(公告)日：2022-05-10

申请号：US16866594

申请日：2020-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Jae Gwon Jang ,  Gwang Jae Jeon

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29

Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

公开(公告)号：US11322368B2

公开(公告)日：2022-05-03

申请号：US17037003

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Seok Hyun Lee ,  Jae Gwon Jang ,  Gwang Jae Jeon

IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US11373980B2

公开(公告)日：2022-06-28

申请号：US16744623

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Youn Kim ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

公开(公告)号：US20210020608A1

公开(公告)日：2021-01-21

申请号：US16744623

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Youn KIM ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.