公开(公告)号：US11652090B2

公开(公告)日：2023-05-16

申请号：US16885391

申请日：2020-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jun Bae ,  Dong Kyu Kim ,  Jin-Woo Park ,  Seok Hyun Lee

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041

Abstract: A semiconductor package includes a first redistribution layer. A plurality of posts is disposed on the first redistribution layer. A semiconductor chip is disposed on the first redistribution layer between the plurality of posts. A second redistribution layer is formed on the plurality of posts and the semiconductor chip. A first memory stack is disposed on the second redistribution layer. A height of each of the plurality of posts extends from an upper surface of the first redistribution layer to a lower surface of the second redistribution layer.

公开(公告)号：US11515260B2

公开(公告)日：2022-11-29

申请号：US16874284

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Hye Kim ,  Dong Kyu Kim ,  Jung-Ho Park

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.

公开(公告)号：US20200273804A1

公开(公告)日：2020-08-27

申请号：US16567790

申请日：2019-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwang Jae JEON ,  Dong Kyu Kim ,  Jung Ho PARK ,  Yeon Ho JANG

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip disposed on the first redistribution structure, a plurality of conductive pillars disposed on the first redistribution structure, an encapsulant covering an upper surface of the first redistribution structure, and a second redistribution structure disposed on the encapsulant. The encapsulant has an upper surface having openings that expose upper surface of the plurality of conductive pillars. The second redistribution structure includes a wiring pattern and connection vias connecting the wiring pattern to the plurality of conductive pillars. An inner side surface of an opening extends vertically from a side surface of the conductive pillar.

公开(公告)号：US12009277B2

公开(公告)日：2024-06-11

申请号：US17866866

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Kyu Kim ,  Jung-Ho Park ,  Jong Youn Kim ,  Yeon Ho Jang ,  Jae Gwon Jang

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/3675 ,  H01L21/4871 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

公开(公告)号：US10455408B2

公开(公告)日：2019-10-22

申请号：US15609489

申请日：2017-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon Sup Kwak ,  Chunping Gong ,  Hyun Do Lee ,  Jin Koo Kang ,  Jin Uk Kang ,  Dong Kyu Kim ,  Jin Wook Kim ,  Hyun Jung Baek ,  Ji Ho Shin ,  Sung Taek Lee

IPC: H04W4/60 ,  H04W4/50 ,  H04W8/18 ,  H04M15/00 ,  H04W64/00 ,  H04W4/24 ,  H04W12/06 ,  H04W8/20 ,  H04M17/02 ,  H04W88/06

Abstract: An electronic device is provided. The electronic device includes a processor configured to execute a roaming application, a communication circuit configured to enable a first subscriber identity module (SIM) and to communicate with a network based on the first SIM, and a memory configured to store data associated with the roaming application. The processor is further configured to, when a roaming service product is selected in the roaming application, download a second SIM corresponding to the roaming service product from a server and enable an activation menu of the roaming service product included in the roaming application, based on location information of the electronic device.

公开(公告)号：US11373980B2

公开(公告)日：2022-06-28

申请号：US16744623

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Youn Kim ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

公开(公告)号：US20210020608A1

公开(公告)日：2021-01-21

申请号：US16744623

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Youn KIM ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.