-
公开(公告)号：US10309987B2
公开(公告)日：2019-06-04
申请号：US15706996
申请日：2017-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yu-Kyum Kim , Gyu-Yeol Kim , Jae-Won Kim
Abstract: A probe includes a beam and at least two tips. The beam transmits test signals to a device under test (DUT). The at least two tips are arranged on a first end portion of the beam in a direction at a predetermined angle to a length direction of the beam and contacts adjacent terminals of the DUT. The beam has a larger width that exceeds a sum of widths of the at least two tips in a width direction of the beam such that the probe has an improved current carrying capacity and is prevented from being damaged due to overcurrent.
-
公开(公告)号：US20190378590A1
公开(公告)日：2019-12-12
申请号：US16244890
申请日：2019-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNG-HO JOO , Gyu-Yeol Kim , Jae-Young Lee , Chang-Hyun Cho
IPC: G11C29/56 , G11C29/10 , G01R31/3183 , G01R31/317
Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.
-
公开(公告)号：US10996242B2
公开(公告)日：2021-05-04
申请号：US15615084
申请日：2017-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gyu-Yeol Kim , Shin-Ho Kang
Abstract: A probe card, for testing an electrical characteristic of a device under test (DUT) including a plurality of semiconductor devices, includes a substrate, a first probe pin disposed on a surface of the substrate and including a tip portion capable of contacting a pad of the DUT, and a second probe pin disposed on the surface of the substrate and including a tip portion capable of contacting the pad of the DUT. The first probe pin protrudes further than the second probe pin protrudes from the surface of the substrate in a first direction that is substantially perpendicular to the surface of the substrate.
-
公开(公告)号：US10811118B2
公开(公告)日：2020-10-20
申请号：US16244890
申请日：2019-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Ho Joo , Gyu-Yeol Kim , Jae-Young Lee , Chang-Hyun Cho
IPC: G01R31/3183 , G11C29/56 , G01R31/317 , G11C29/10
Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.
-
-
-
Search Results
4
records
(took 0.049 seconds)
