公开(公告)号：US20160365409A1

公开(公告)日：2016-12-15

申请号：US15159809

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02

CPC classification number: H01L28/90 ,  H01L27/10852

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract translation: 电容器结构包括彼此水平间隔开的多个底部电极，覆盖底部电极的侧壁的支撑结构，围绕支撑结构的顶部电极和底部电极，以及插入支撑结构和顶部之间的电介质层 电极，以及顶部电极和每个底部电极之间。 支撑结构的最上表面位于比每个底部电极的最上表面更高的水平面上。

公开(公告)号：US20140030867A1

公开(公告)日：2014-01-30

申请号：US13953917

申请日：2013-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYONGSOO KIM ,  Joon KIM ,  WonSeok YOO

IPC: H01L21/027

CPC classification number: H01L21/027 ,  G03F9/708 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask.

Abstract translation: 制造半导体器件的方法包括在具有对准键的衬底上形成蚀刻目标层，在蚀刻目标层上形成透明的第一图案以面对对准键，在蚀刻靶层上形成不透明的第二图案 与第一图案相邻，并且使用第一图案和第二图案作为蚀刻掩模蚀刻蚀刻目标层。

公开(公告)号：US20200176556A1

公开(公告)日：2020-06-04

申请号：US16787426

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

公开(公告)号：US20210183994A1

公开(公告)日：2021-06-17

申请号：US17156773

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

公开(公告)号：US20180182843A1

公开(公告)日：2018-06-28

申请号：US15897931

申请日：2018-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/90 ,  H01L27/10852

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.