公开(公告)号：US11205601B2

公开(公告)日：2021-12-21

申请号：US16747404

申请日：2020-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eung chang Lee ,  Heeyoub Kang ,  Haejung Yang ,  Youngrok Oh ,  Kitaek Lee ,  Bong jae Lee

IPC: H01L23/29 ,  H01L23/367 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  C08G77/04

Abstract: A semiconductor package includes a semiconductor chip and a polydimethylsiloxane (PDMS) layer that is provided on the semiconductor chip and of which upper surface is exposed to the outside. Since the semiconductor package may include the PDMS layer, heat emitting performance of the semiconductor package in a vacuum state may improve.

公开(公告)号：US20220334940A1

公开(公告)日：2022-10-20

申请号：US17510634

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haejung Yang ,  Heeyoub Kang ,  Youngrok Oh ,  Kitaek Lee ,  Heechul Lee

IPC: G06F11/30 ,  G06F11/34

Abstract: A storage device includes at least one non-volatile memory device, a first temperature sensor and a second temperature sensor arranged adjacent to the at least one non-volatile memory device, and a controller controlling an operation performance level of the at least one non-volatile memory device based on a plurality of performance tables, a first temperature detected by the first temperature sensor, and a second temperature detected by the second temperature sensor. Each performance table includes a plurality of entries, and each entry includes information regarding the operation performance level of the at least one non-volatile memory device. Each performance table corresponds to a result of a calculation regarding the first temperature and the second temperature.

公开(公告)号：US11681599B2

公开(公告)日：2023-06-20

申请号：US17510634

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haejung Yang ,  Heeyoub Kang ,  Youngrok Oh ,  Kitaek Lee ,  Heechul Lee

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3034 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3466

Abstract: A storage device includes at least one non-volatile memory device, a first temperature sensor and a second temperature sensor arranged adjacent to the at least one non-volatile memory device, and a controller controlling an operation performance level of the at least one non-volatile memory device based on a plurality of performance tables, a first temperature detected by the first temperature sensor, and a second temperature detected by the second temperature sensor. Each performance table includes a plurality of entries, and each entry includes information regarding the operation performance level of the at least one non-volatile memory device. Each performance table corresponds to a result of a calculation regarding the first temperature and the second temperature.