公开(公告)号：US20250072001A1

公开(公告)日：2025-02-27

申请号：US18800667

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeol LEE ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes: a peripheral circuit structure including a substrate and a circuit that is disposed on the substrate; a cell structure disposed on the peripheral circuit structure and including gate electrodes and a channel that extends through the gate electrodes; and a bonding structure located between the peripheral circuit structure and the cell structure, wherein the bonding structure includes: a first insulating layer attached to the peripheral circuit structure; a first bonding pad disposed on the peripheral circuit structure and electrically connected to the circuit; a second insulating layer attached to the cell structure; a second bonding pad disposed on the cell structure and electrically connected to the gate electrodes; and an anisotropic conductive adhesive layer located between the first insulating layer and the second insulating layer and between the first bonding pad and the second bonding pad, and including a plurality of conductive particles.

公开(公告)号：US20250107086A1

公开(公告)日：2025-03-27

申请号：US18737295

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanbyeol LEE ,  Younghwan SON ,  Sangdon LEE ,  Shinhwan KANG ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.