公开(公告)号：US20230012115A1

公开(公告)日：2023-01-12

申请号：US17570874

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

公开(公告)号：US20240396585A1

公开(公告)日：2024-11-28

申请号：US18794634

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujae JANG ,  Hyeyong GO ,  Jungjoon KIM ,  Jihun KIM ,  Hyoungtak SON ,  Yeonsang YUN ,  Sangdon LEE ,  Jihyeon JANG ,  Sungyoul CHO

IPC: H04B1/40 ,  G01R19/165 ,  H02M3/158 ,  H03F1/30

Abstract: Disclosed are a method for controlling a voltage supplied to a radio frequency (RF) transmission/reception module, and an electronic device for carrying out same. The electronic device, according to an embodiment, comprises: a communication processor including at least one processor comprising processing circuitry; an RF integrated circuit configured to generate a RF signal by processing data received from the communication processor, and transmit the RF signal to a RF transmission/reception module; the RF transmission/reception module comprising an amplification circuit configured to amplify the RF signal, and an overvoltage protection circuit configured to reduce overvoltage-induced damage to the amplification circuit, and configured to transmit the amplified RF signal; and a power management integrated circuit configured to manage power supplied to the amplification circuit using a voltage converter comprising a boost circuit configured to step up a voltage input into the boost circuit and a buck circuit configured to step down a voltage input into the buck circuit, wherein at least one processor of the communication processor, individually and/or collectively, is configured to: use the overvoltage protection circuit to detect the occurrence of an overshoot in which a voltage supplied to the RF transmission/reception module exceeds a threshold value, and in response to detecting the occurrence of the overshoot, control the power management integrated circuit and thus reduce an operation time of the boost circuit.

公开(公告)号：US20230024655A1

公开(公告)日：2023-01-26

申请号：US17858388

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Joonsung KIM ,  Jiwon KIM ,  Jaeho KIM ,  Sukkang SUNG ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.

公开(公告)号：US20250107086A1

公开(公告)日：2025-03-27

申请号：US18737295

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanbyeol LEE ,  Younghwan SON ,  Sangdon LEE ,  Shinhwan KANG ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.

公开(公告)号：US20240275638A1

公开(公告)日：2024-08-15

申请号：US18629184

申请日：2024-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohun KIM ,  Kyujae JANG ,  Jaemoon CHA ,  Jimin KOO ,  Jaegon GHIM ,  Jungsuk WOO ,  Yeonsang YUN ,  Kwangsu LEE ,  Deokhee LEE ,  Sangdon LEE ,  Yeonjoo LEE ,  Sanghyun CHANG ,  Sungyoul CHO ,  Hyunkyung JO

IPC: H04L25/02 ,  H04L5/00

CPC classification number: H04L25/0204 ,  H04L5/0023 ,  H04L5/0048

Abstract: Disclosed are a transmission power control method and an electronic device for performing the same. The transmission power control method according to various embodiments may comprise: determining whether the magnitude of a reference signal received from a first base station for transmitting and receiving a first signal is greater than or equal to a set magnitude; determining a ratio of a specific absorption rate of the first signal according to a ratio set in the total specific absorption rate margin; and transmitting the first signal on the basis of the ratio of the specific absorption rate of the first signal.

公开(公告)号：US20230109996A1

公开(公告)日：2023-04-13

申请号：US17955696

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon SON ,  Sukkang SUNG ,  Sangdon LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

公开(公告)号：US20220375959A1

公开(公告)日：2022-11-24

申请号：US17552812

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Jiwon KIM ,  Sung-Min HWANG ,  Sukkang SUNG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.