公开(公告)号：US20240153886A1

公开(公告)日：2024-05-09

申请号：US18225447

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haseob Seong ,  Seungduk Baek ,  Ae-Nee Jang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08146

Abstract: A semiconductor package includes a substrate including a substrate pad and plural vias, the substrate having a first trench on a top surface of the substrate, and a chip stack on the substrate that includes semiconductor chips. A chip pad of a first semiconductor chip, which is a lowermost one of the semiconductor chips, is bonded to the substrate pad of the substrate. The chip pad and the substrate pad are formed of a same metallic material. The first trench overlaps with a corner of the first semiconductor chip, when viewed in plan view.

公开(公告)号：US20250069972A1

公开(公告)日：2025-02-27

申请号：US18658652

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haseob Seong ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Provided is a semiconductor package including a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips each including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, and a package molding layer including a bottom molding portion on a portion of an upper surface of the first semiconductor chip, which is exposed by the lowermost second semiconductor chip, and a side molding portion on side walls of the plurality of second semiconductor chips, wherein the side molding portion of the package molding layer extends in a vertical direction from an edge of an upper surface of the bottom molding portion of the package molding layer.

公开(公告)号：US20250087607A1

公开(公告)日：2025-03-13

申请号：US18773068

申请日：2024-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONMIN LEE ,  Haseob Seong ,  MINSEUNG JI

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip, a dummy die on the first semiconductor chip, second semiconductor chips stacked on the dummy die, and a dummy plate on the second semiconductor chips. Each of the first semiconductor chip, the dummy die, and the second semiconductor chips includes through-electrodes. The dummy die and the second semiconductor chip closest to the dummy die are connected to each other by direct contact of bonding pads. Adjacent ones of the second semiconductor chips are connected to each other by direct contact of bonding pads. The first semiconductor chip, the dummy die, the second semiconductor chip, and the dummy plate have a first width, a second width, a third width, and a fourth width in a horizontal direction, respectively. The fourth width is greater than the second width and the third width.

公开(公告)号：US20240264393A1

公开(公告)日：2024-08-08

申请号：US18235518

申请日：2023-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Geun Ahn ,  Haseob Seong

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/4249 ,  G02B6/4293

Abstract: Disclosed is a silicon photonics package including an interposer including embedded optical components; a light source element optically connected to the optical components; a first semiconductor chip on a top surface of the interposer; a first redistribution layer on a bottom surface of the interposer; a second semiconductor chip on the first redistribution layer; a second redistribution layer on the first redistribution layer and being electrically connected to the first redistribution layer; conductive metal posts provided between the first and second redistribution layers; a mold material filling a space between the first and second redistribution layers; and a solder bump array on a bottom surface of the second redistribution layer. The top surface of the interposer includes an exposure area to which an optical fiber array is directly attached, in which an optical signal is directly transmitted between the optical components and the optical fiber array through the exposure area.