公开(公告)号：US11636894B2

公开(公告)日：2023-04-25

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/419 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4099 ,  G11C11/4094

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

公开(公告)号：US20220148644A1

公开(公告)日：2022-05-12

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C5/06

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.