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1.发明授权公开(公告)号：US10862526B2
公开(公告)日：2020-12-08
申请号：US16592525
申请日：2019-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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Patent Agency Ranking
2.发明授权公开(公告)号：US10050661B2
公开(公告)日：2018-08-14
申请号：US15614667
申请日：2017-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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公开(公告)号：US11507131B2
公开(公告)日：2022-11-22
申请号：US17188013
申请日：2021-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ho-Rang Jang , Ji-Woong Kwon , Sang-Wook Han
Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.
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4.发明授权公开(公告)号：US10476547B2
公开(公告)日：2019-11-12
申请号：US16037024
申请日：2018-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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公开(公告)号：US10936009B2
公开(公告)日：2021-03-02
申请号：US16165447
申请日：2018-10-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ho-Rang Jang , Ji-Woong Kwon , Sang-Wook Han
Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.
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6.发明授权公开(公告)号：US10516433B2
公开(公告)日：2019-12-24
申请号：US16037024
申请日：2018-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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