公开(公告)号：US20150303214A1

公开(公告)日：2015-10-22

申请号：US14682567

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Soo KIM ,  Sung-Hoi HUR ,  So-Wi CHIN

IPC: H01L27/115 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42356 ,  H01L29/78 ,  H01L29/7827

Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

Abstract translation: 一种垂直存储装置，包括：包括单元区域和外围电路区域的基板，所述外围电路区域包括栅极结构，所述栅极结构包括晶体管，所述单元区域上的多个沟道，每个所述沟道沿垂直于第一方向延伸 相对于衬底的顶表面，沿着第一方向堆叠并且彼此间隔开的多个栅极线，围绕沟道的外侧壁的栅极线以及电池区域和外围电路区域之间的阻挡结构 ，其中所述阻挡结构的高度大于所述外围区域中的所述栅极结构的高度。

公开(公告)号：US20150147858A1

公开(公告)日：2015-05-28

申请号：US14567345

申请日：2014-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hoon KIM ,  Hong-Soo KIM ,  Hoo-Sung CHO

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66825 ,  H01L21/76232 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66833

Abstract: A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extend in a first direction and are arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connect at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction.

Abstract translation: 非易失性存储器件包括：衬底，其包括有源区域和场区域，有源区域上的选择晶体管和单元晶体管，桥接部分上的位线接触，以及电连接到位线触点的共享位线。 有源区域包括串部分和桥接部分。 弦线部分沿第一方向延伸并且布置在基本上垂直于第一方向的第二方向上，并且桥接部分连接至少两个相邻的线部分。 每个桥接部分具有在第一方向上的长度等于或大于每个位线接触件在第一方向上的宽度的大约两倍。

公开(公告)号：US20200251494A1

公开(公告)日：2020-08-06

申请号：US16856611

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hoon KIM ,  Hong-Soo KIM ,  Ju-Yeon LEE

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11556

Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.