公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US10152114B2

公开(公告)日：2018-12-11

申请号：US15223568

申请日：2016-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Chung Byun

IPC: G06F1/00 ,  G06F1/32 ,  G11C5/14 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/08 ,  G11C29/20 ,  G11C29/50

Abstract: A memory module includes a counter configured to count a number of commands received from a host to generate a counted number and provide the counted value to the host, a memory device configured to receive an operating frequency and an operating voltage from that host that are determined based on the counted number, and a serial presence detect (SPD) configured to store the operating frequency and operating voltage.