公开(公告)号：US20220014195A1

公开(公告)日：2022-01-13

申请号：US17160888

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwang Ho CHOI ,  Yungeun NAM ,  Sodam JU

IPC: H03K19/0185 ,  H04L25/02 ,  G11C11/4093 ,  G11C7/10

Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node, supplying a third power supply voltage, through a first variable resistor and connected to a fourth power supply node, supplying a fourth power supply voltage, lower than the third power supply node, through a second variable resistor.

公开(公告)号：US20160105273A1

公开(公告)日：2016-04-14

申请号：US14712261

申请日：2015-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwang Ho CHOI ,  Jongshin SHIN ,  Seung-Hee YANG ,  Chang-Kyung SEONG

IPC: H04L7/00 ,  H04L7/033 ,  H04L7/04

CPC classification number: H03L7/18 ,  H03M9/00 ,  H04L1/00

Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.

Abstract translation: 提供了一种用于驱动SERDES电路的方法，其可以减少SERDES电路的空间的浪费。 电路驱动方法包括从向串行器/解串器（SERDES）电路提供时钟信号的公共锁相环（PLL）产生公共时钟信号，将公共时钟信号分配给睁眼监视器和数据传输通道 SERDES电路，并使用公共时钟信号驱动睁眼监视器和数据传输通道。