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公开(公告)号：US20240267138A1
公开(公告)日：2024-08-08
申请号：US18431087
申请日：2024-02-02
发明人： Yungeun NAM , Hobin SONG , Hyogyuem RHEW , Jaehyun PARK , Jongshin SHIN
CPC分类号： H04B17/297 , H04B17/19 , H04B17/295
摘要： A transceiver according to an aspect of the inventive concepts may include a transmitter, a first receiver pad configured to receive a first external voltage, a second receiver pad configured to receive a second external voltage, a receiver configured to generate a test target signal based on the first external voltage and the second external voltage, and a digital logic configured to perform a loopback test on a reception path of a data signal by transmitting the data signal and receiving the test target signal.
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2.发明申请METHODS OF GENERATING A PIXEL CLOCK SIGNAL FROM A TRANSMISSION CLOCK SIGNAL AND RELATED DATA TRANSMISSION METHODS FOR MULTIMEDIA SOURCES 审中-公开从传输时钟信号生成像素时钟信号的方法和多媒体源的相关数据传输方法公开(公告)号：US20130113992A1
公开(公告)日：2013-05-09
申请号：US13729076
申请日：2012-12-28
发明人： Jongshin SHIN
IPC分类号： H04N5/04
CPC分类号： H04N5/067 , G09G5/008 , G09G5/12 , G09G2370/04 , G09G2370/12 , H04N5/04 , H04N5/38 , H04N5/775 , H04N21/242 , H04N21/8547
摘要： Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal. The pixel clock signal has a third frequency that is the product of the second frequency and the multiple,
摘要翻译： 提供了生成用于多媒体源的像素时钟信号的方法，其中从具有第二频率的参考时钟信号产生具有第一频率的传输时钟信号。 将所生成的传输时钟信号乘以倍数以产生像素时钟信号。 像素时钟信号具有作为第二频率和倍数的乘积的第三频率，
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公开(公告)号：US20160294381A1
公开(公告)日：2016-10-06
申请号：US15048412
申请日：2016-02-19
发明人： Kangjik Kim , Sanghune PARK , Jaehyun PARK , Jongshin SHIN
IPC分类号： H03K17/28 , H03K5/1534 , H04L7/04 , H03K5/08
CPC分类号： H04L7/04 , H03K5/08 , H03K5/1534 , H03K5/22 , H03K17/14 , H04L25/0272 , H04L25/0278 , H04L25/028
摘要： Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.
摘要翻译： 提供电压模式驱动器和具有该电压模式驱动器的电子设备。 电压模式驱动器可以包括电压调节器和纹波补偿单元，其连接到电压调节器的输出端，并被配置为与时钟信号同步地将数据模式的当前数据位与数据模式的先前数据位进行比较 输入到纹波补偿单元，当当前数据位等于先前的数据位时产生控制信号，并且响应于控制信号向输出端施加接地电压。
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公开(公告)号：US20160105273A1
公开(公告)日：2016-04-14
申请号：US14712261
申请日：2015-05-14
摘要： Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.
摘要翻译： 提供了一种用于驱动SERDES电路的方法，其可以减少SERDES电路的空间的浪费。 电路驱动方法包括从向串行器/解串器（SERDES）电路提供时钟信号的公共锁相环（PLL）产生公共时钟信号，将公共时钟信号分配给睁眼监视器和数据传输通道 SERDES电路，并使用公共时钟信号驱动睁眼监视器和数据传输通道。
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公开(公告)号：US20220200605A1
公开(公告)日：2022-06-23
申请号：US17503802
申请日：2021-10-18
发明人： Wonsuk JANG , Hanseok KIM , Jaehyun PARK , Hobin SONG , Jongshin SHIN , Youngjin CHUNG
摘要： An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.
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公开(公告)号：US20220190869A1
公开(公告)日：2022-06-16
申请号：US17384991
申请日：2021-07-26
发明人： Younwoong CHUNG , Yungeun NAM , Jongshin SHIN
摘要： Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.
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公开(公告)号：US20160013927A1
公开(公告)日：2016-01-14
申请号：US14489986
申请日：2014-09-18
发明人： June-Hee LEE , Jongshin SHIN , Youngkyun JEONG , Dongchul CHOI
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H04L27/22
摘要： A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.
摘要翻译： 时钟数据恢复电路包括：采样器，用于对输入的数据位进行采样;相位检测器，用于根据采样的输入数据产生边沿位置信号和极性信号;有限状态机，用于保存当前边沿位置状态;极性判定单元 产生极性反转信号以反转极性信号，增益控制器产生跟踪带宽信号;恢复环路，被配置为调整参考时钟的边沿偏移;以及位选择器，被配置为恢复输入数据。 时钟数据恢复电路在第一操作模式下具有第一等待时间，在第二操作模式下具有第二等待时间。 时钟数据恢复电路中的相位检测器可以包括第一相位检测器和第二检测器，其组合在一起，用于时钟数据恢复电路的低等待时间和低锁定时间。
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