公开(公告)号：US11901187B2

公开(公告)日：2024-02-13

申请号：US17522193

申请日：2021-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanyeol Park ,  Jongyoung Park ,  Yongdeok Lee ,  Sejin Kyung ,  Daewee Kong ,  Ilwoo Kim ,  Songyi Baek ,  Philippe Coche

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/02129 ,  H01L21/76829 ,  H01L28/40 ,  H01L28/60 ,  H01L29/06

Abstract: Provided is a semiconductor device. The semiconductor device includes a wafer; an etch stop layer on the wafer; a lower mold layer on the etch stop layer; an intermediate supporter layer on the lower mold layer; an upper mold layer on the intermediate supporter layer; an upper supporter layer on the upper mold layer; and a hard mask structure on the upper supporter layer, wherein the hard mask structure includes a first hard mask layer on the upper supporter layer and a second hard mask layer on the first hard mask layer, one of the first hard mask layer and the second hard mask layer includes a first organic layer including a SOH containing C, H, O, and N, and the other one of the first hard mask layer and the second hard mask layer includes a second organic layer including an SOH containing C, H, and O.

公开(公告)号：US20220262819A1

公开(公告)日：2022-08-18

申请号：US17648134

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong Kim ,  Junghwan Lee ,  Hwanyeol Park

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes: a semiconductor substrate having a cell region and a dummy region outside the cell region, a plurality of gate electrodes and a plurality of insulating layers, in the cell region, extending in first and second directions parallel to a main surface of the semiconductor substrate and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first and second directions crossing each other, and a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked in the dummy region in the third direction, wherein a carbon concentration of an upper dummy mold layer of the plurality of dummy mold layers is less than a carbon concentration of a lower dummy mold layer of the plurality of dummy mold layers, the lower dummy mold layer being between the upper dummy mold layer and the main surface of the semiconductor substrate.

公开(公告)号：US12302576B2

公开(公告)日：2025-05-13

申请号：US17648134

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong Kim ,  Junghwan Lee ,  Hwanyeol Park

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: An integrated circuit device includes: a semiconductor substrate having a cell region and a dummy region outside the cell region, a plurality of gate electrodes and a plurality of insulating layers, in the cell region, extending in first and second directions parallel to a main surface of the semiconductor substrate and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first and second directions crossing each other, and a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked in the dummy region in the third direction, wherein a carbon concentration of an upper dummy mold layer of the plurality of dummy mold layers is less than a carbon concentration of a lower dummy mold layer of the plurality of dummy mold layers, the lower dummy mold layer being between the upper dummy mold layer and the main surface of the semiconductor substrate.

公开(公告)号：US12225724B2

公开(公告)日：2025-02-11

申请号：US17505842

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanyeol Park ,  Sejin Kyung ,  Ilwoo Kim ,  Minwoo Lee ,  Youngho Jeung

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer and a first sacrificial layer are alternately and repeatedly formed on a substrate to form a mold layer. A sacrificial layer structure is formed on the mold layer to include an etch stop layer and a second sacrificial layer sequentially stacked. After forming a hard mask on the sacrificial layer structure, the sacrificial layer structure and the mold layer are etched by a dry etching process using the hard mask as an etching mask to form a channel hole exposing an upper surface of the substrate and form a recess on a sidewall of the second sacrificial layer adjacent to the channel hole. A memory channel structure is formed in the channel hole. The first sacrificial layer is replaced with a gate electrode.