公开(公告)号：US20220216402A1

公开(公告)日：2022-07-07

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

公开(公告)号：US12279537B2

公开(公告)日：2025-04-15

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.