公开(公告)号：US12279537B2

公开(公告)日：2025-04-15

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

公开(公告)号：US09806204B2

公开(公告)日：2017-10-31

申请号：US14536250

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Soo Ahn ,  O Ik Kwon ,  Bum-Soo Kim ,  Hyun-Sung Kim ,  Kyoung-Sub Shin ,  Min-Kyung Yun ,  Seung-Pil Chung ,  Won-Bong Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/423

CPC classification number: H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

公开(公告)号：US20190280008A1

公开(公告)日：2019-09-12

申请号：US16423680

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Jeong Kim ,  Byoung Jun Choi ,  O Ik Kwon

IPC: H01L27/11582 ,  H01L29/792 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/66

Abstract: A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending through the gate electrode layers in a direction perpendicular to an upper surface of the substrate, cell contacts connected to the gate electrode layers, an active region on a peripheral circuit region of the substrate, planar gate electrode layers on the peripheral circuit region and adjacent to the active region, a cover layer on the active region, and peripheral contacts connected to the active region and the planar gate electrode layers. At least a portion of the peripheral contacts are separated from the cover layer above the planar gate electrode layers.

公开(公告)号：US09853048B2

公开(公告)日：2017-12-26

申请号：US15226329

申请日：2016-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Jeong Kim ,  O Ik Kwon ,  Jong Kyoung Park ,  Su Jee Sunwoo

IPC: H01L29/76 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.

公开(公告)号：US20220216402A1

公开(公告)日：2022-07-07

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.