公开(公告)号：US09324574B2

公开(公告)日：2016-04-26

申请号：US14578723

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun Seung Kang

IPC: H01L21/311 ,  H01L21/469 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/32139

Abstract: Methods of forming a pattern in a semiconductor device may be provided. The methods may include sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer including first and second regions, forming a first spacer layer on the second hard mask layer, forming a second hard mask pattern layer by etching the second hard mask layer using the first spacer layer, forming a second spacer layer on a sidewall of the second hard mask pattern layer, forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer, and etching the etching target layer using the first hard mask pattern layer.

Abstract translation: 可以提供在半导体器件中形成图案的方法。 所述方法可以包括在包括第一和第二区域的蚀刻目标层上顺序形成第一硬掩模层和第二硬掩模层，在第二硬掩模层上形成第一间隔层，通过蚀刻形成第二硬掩模图案层 使用所述第一间隔层的第二硬掩模层，在所述第二硬掩模图案层的侧壁上形成第二间隔层，通过使用所述第二间隔层蚀刻所述第一硬掩模层来形成第一硬掩模图案层，以及蚀刻所述蚀刻 目标层使用第一硬掩模图案层。

公开(公告)号：US20220216402A1

公开(公告)日：2022-07-07

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

公开(公告)号：US12279537B2

公开(公告)日：2025-04-15

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.