公开(公告)号：US09773806B1

公开(公告)日：2017-09-26

申请号：US15390977

申请日：2016-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Kyung Jun Shin ,  Dong Seog Eun ,  Ji Hye Kim ,  Hyun Kook Lee

IPC: H01L21/8239 ,  H01L27/115 ,  H01L27/11582 ,  H01L27/11568 ,  G11C16/24 ,  G11C16/04 ,  H01L21/8238

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/823885 ,  H01L21/8239 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

公开(公告)号：US20190115366A1

公开(公告)日：2019-04-18

申请号：US16212240

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNG IL LEE ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

公开(公告)号：US10211220B2

公开(公告)日：2019-02-19

申请号：US15688011

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Kyung Jun Shin ,  Dong Seog Eun ,  Ji Hye Kim ,  Hyun Kook Lee

IPC: H01L27/115 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/1157 ,  H01L21/8239 ,  H01L21/8238 ,  H01L27/11568

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

公开(公告)号：US10204919B2

公开(公告)日：2019-02-12

申请号：US15252740

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.