公开(公告)号：US10854622B2

公开(公告)日：2020-12-01

申请号：US16886021

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Bae Yoon ,  Joong-Shik Shin ,  Kwang-Ho Kim ,  Hyun-Mog Park

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/11575

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

公开(公告)号：US20190035805A1

公开(公告)日：2019-01-31

申请号：US15941917

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Il Lee ,  Ji-Mo Gu ,  Hyun-Mog Park ,  Tak Lee ,  Jun-Ho Cha ,  Sang-Jun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

公开(公告)号：US11011536B2

公开(公告)日：2021-05-18

申请号：US15941917

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Il Lee ,  Ji-Mo Gu ,  Hyun-Mog Park ,  Tak Lee ,  Jun-Ho Cha ,  Sang-Jun Hong

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/10 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

公开(公告)号：US10937756B2

公开(公告)日：2021-03-02

申请号：US16402747

申请日：2019-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Mog Park

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/544 ,  H01L21/67 ,  H01L21/68 ,  H01L21/306 ,  H01L21/268

Abstract: In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.