公开(公告)号：US20220351763A1

公开(公告)日：2022-11-03

申请号：US17536282

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsik Yoo ,  Hyunah An

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/14

Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

公开(公告)号：US12237833B2

公开(公告)日：2025-02-25

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H03K19/20 ,  H04L25/49

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.

公开(公告)号：US20230155575A1

公开(公告)日：2023-05-18

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H04L25/49 ,  H03K19/20

CPC classification number: H03K3/017 ,  H04L25/4902 ,  H03K19/20

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.

公开(公告)号：US11615824B2

公开(公告)日：2023-03-28

申请号：US17536282

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsik Yoo ,  Hyunah An

IPC: G11C7/22 ,  G11C5/14 ,  G11C7/10

Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

公开(公告)号：US11159149B2

公开(公告)日：2021-10-26

申请号：US17021367

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Jang-Woo Ryu ,  Hyunah An ,  Hangi Jung

IPC: H03L5/00 ,  H03K3/356 ,  G11C7/22

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.