公开(公告)号：US20190140628A1

公开(公告)日：2019-05-09

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： WANGSOO KIM ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-dae Choi

IPC: H03K5/13

CPC classification number: H03K5/13 ,  H03K2005/00019 ,  H04B1/04

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

公开(公告)号：US10069495B2

公开(公告)日：2018-09-04

申请号：US15594107

申请日：2017-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hangi Jung ,  Hun-Dae Choi ,  Jinhyeok Baek

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/408

Abstract: A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

公开(公告)号：US20250157513A1

公开(公告)日：2025-05-15

申请号：US19021918

申请日：2025-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US20240111695A1

公开(公告)日：2024-04-04

申请号：US18538263

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20230368824A1

公开(公告)日：2023-11-16

申请号：US18052976

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/225

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US10367490B2

公开(公告)日：2019-07-30

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wangsoo Kim ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-Dae Choi

IPC: H03K5/13 ,  H04B1/04 ,  H03K5/00

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

公开(公告)号：US12237049B2

公开(公告)日：2025-02-25

申请号：US18052976

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US11567886B2

公开(公告)日：2023-01-31

申请号：US17008121

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US11159149B2

公开(公告)日：2021-10-26

申请号：US17021367

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Jang-Woo Ryu ,  Hyunah An ,  Hangi Jung

IPC: H03L5/00 ,  H03K3/356 ,  G11C7/22

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

公开(公告)号：US11874784B2

公开(公告)日：2024-01-16

申请号：US18089148

申请日：2022-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.