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1.发明授权公开(公告)号：US11335431B2
公开(公告)日：2022-05-17
申请号：US17216160
申请日：2021-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun Kim , Yoon-Na Oh , Hyung-Jin Kim , Hui-Kap Yang , Jang-Woo Ryu
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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公开(公告)号：US11189333B2
公开(公告)日：2021-11-30
申请号：US16939028
申请日：2020-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jang-Woo Ryu , Soojung Rho
IPC: G11C5/14 , G11C11/4074 , G11C11/4076 , H03L7/081 , G11C7/06 , G11C5/02
Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.
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公开(公告)号：US10553273B2
公开(公告)日：2020-02-04
申请号：US16032822
申请日：2018-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jang-Woo Ryu , Kyungryun Kim , Soo Hwan Kim , Huikap Yang
IPC: G11C7/00 , G11C11/4091 , G11C7/06 , G11C7/18 , G11C8/08 , G11C11/4097 , G11C11/4093
Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.
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4.发明授权公开(公告)号：US10971247B2
公开(公告)日：2021-04-06
申请号：US16283650
申请日：2019-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun Kim , Yoon-Na Oh , Hyung-Jin Kim , Hui-Kap Yang , Jang-Woo Ryu
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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公开(公告)号：US10318469B2
公开(公告)日：2019-06-11
申请号：US14620219
申请日：2015-02-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min-Soo Jang , Gong-Heum Han , Chul-Sung Park , Jang-Woo Ryu , Chang-Yong Lee , Tae-Seong Jang
Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240135985A1
公开(公告)日：2024-04-25
申请号：US18297908
申请日：2023-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Jang-Woo Ryu
IPC: G11C11/4076 , G06F1/12 , G11C11/408 , H03K3/037 , H03K19/20
CPC classification number: G11C11/4076 , G06F1/12 , G11C11/4087 , H03K3/037 , H03K19/20
Abstract: A semiconductor device includes a chip select signal flip-flop configured to: latch a chip select signal in-sync with a first propagation clock signal, and output a first chip select enable signal, and latch the chip select signal in-sync with a second propagation clock signal having a phase opposite to a phase of the first propagation clock signal, and output a second chip select enable signal; and a clock control circuit configured to generate the first propagation clock signal and the second propagation clock signal based on a clock signal, and selectively output one of the first propagation clock signal and the second propagation clock signal based on an enable level of the first chip select enable signal and an enable level of the second chip select enable signal.
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公开(公告)号：US09099196B2
公开(公告)日：2015-08-04
申请号：US14141233
申请日：2013-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jang-Woo Ryu , Young-Dae Lee
IPC: G11C11/00 , G11C11/406 , G11C11/4074
CPC classification number: G11C11/40626 , G11C11/4074
Abstract: A method of operating a semiconductor memory device is disclosed. The method may include receiving an access command, applying a first voltage to a selected word line of the semiconductor memory device for a period of time in response to receiving the access command, applying a second voltage to word lines adjacent to the selected word line before and after the period of time, and applying a third voltage to the word lines adjacent to the selected word line for the period of time, a voltage level of the third voltage greater than the second voltage. The applying the third voltage may occur when the semiconductor memory device is operated at a temperature below the predetermined temperature.
Abstract translation: 公开了一种操作半导体存储器件的方法。 该方法可以包括接收访问命令，响应于接收到访问命令，将半导体存储器件的选定字线施加第一电压一段时间，将第二电压施加到与选定字线相邻的字线之前 并且在所述时间段之后，并且对于与所选择的字线相邻的字线在一段时间内施加第三电压，所述第三电压的电压电平大于所述第二电压。 当半导体存储器件在低于预定温度的温度下工作时，施加第三电压可能发生。
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公开(公告)号：US20250157513A1
公开(公告)日：2025-05-15
申请号：US19021918
申请日：2025-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Lee , Daehyun Kwon , Jang-Woo Ryu , Hangi Jung
IPC: G11C7/22 , G11C7/10 , G11C11/4076 , G11C11/4093
Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.
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9.发明公开公开(公告)号：US20230368824A1
公开(公告)日：2023-11-16
申请号：US18052976
申请日：2022-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Lee , Daehyun Kwon , Jang-Woo Ryu , Hangi Jung
CPC classification number: G11C7/222 , G11C7/1093 , G11C7/1096 , G11C7/225
Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.
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10.发明授权公开(公告)号：US11626185B2
公开(公告)日：2023-04-11
申请号：US17723200
申请日：2022-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun Kim , Yoon-Na Oh , Hyung-Jin Kim , Hui-Kap Yang , Jang-Woo Ryu
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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