公开(公告)号：US20250149077A1

公开(公告)日：2025-05-08

申请号：US18937774

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Yoon ,  Jaemin Choi ,  ChangSik Yoo ,  Ki-Heung Kim ,  Hoseok Seol ,  Youngdo Um ,  Hyongryol Hwang

IPC: G11C8/18 ,  G11C8/06 ,  H03K19/173 ,  H03K21/08

Abstract: An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

公开(公告)号：US12237833B2

公开(公告)日：2025-02-25

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H03K19/20 ,  H04L25/49

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.

公开(公告)号：US20230155575A1

公开(公告)日：2023-05-18

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H04L25/49 ,  H03K19/20

CPC classification number: H03K3/017 ,  H04L25/4902 ,  H03K19/20

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.