公开(公告)号：US12143107B2

公开(公告)日：2024-11-12

申请号：US17812242

申请日：2022-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Ah An ,  Chang Sik Yoo ,  Jin Kwan Park ,  Sung Woo Yoon

IPC: H03K19/173 ,  H03K19/0185 ,  H03K19/17788

Abstract: A multiplexer includes a first inverter for receiving and inverting first data, a second inverter for receiving and inverting second data, and a first driver connected to an output of the first inverter and to an output of the second inverter. The first driver is configured to output the first data or the second data as output data.

公开(公告)号：US12237833B2

公开(公告)日：2025-02-25

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H03K19/20 ,  H04L25/49

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.

公开(公告)号：US20230155575A1

公开(公告)日：2023-05-18

申请号：US18045578

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Yoon ,  Jin Kwan Park ,  Hyunah An

IPC: H03K3/017 ,  H04L25/49 ,  H03K19/20

CPC classification number: H03K3/017 ,  H04L25/4902 ,  H03K19/20

Abstract: A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.