-
公开(公告)号：US09589625B2
公开(公告)日：2017-03-07
申请号：US14742821
申请日：2015-06-18
发明人： Hyun-Ki Kim , Hyung-Sik You
IPC分类号： G11C11/24 , G11C7/00 , G11C11/4074 , G11C11/406 , G11C11/4091 , G11C7/06 , G11C7/08 , G11C11/4094
CPC分类号： G11C11/4074 , G11C7/065 , G11C7/08 , G11C11/406 , G11C11/40611 , G11C11/4091 , G11C11/4094 , G11C2211/4065 , G11C2211/4068
摘要： A method of operating a memory device may include: providing a first power supply voltage to a sense amplifier during a first time interval, the first time interval being between a first time at which a voltage is provided to a first bit line, and a second time at which a pre-charge command is received; and providing a second power supply voltage to the sense amplifier during a second time interval, during which the word line is enabled after the pre-charge command is received. The second power supply voltage may be greater than the first power supply voltage.
摘要翻译： 操作存储器件的方法可以包括：在第一时间间隔期间向感测放大器提供第一电源电压，第一时间间隔在提供电压到第一位线的第一时间和第二时间间隔之间 接收预充电命令的时间; 以及在第二时间间隔期间向读出放大器提供第二电源电压，在此期间，在接收到预充电命令之后，字线被使能。 第二电源电压可以大于第一电源电压。
-
2.发明授权Bit-line sense amplifier capable of compensating mismatch between transistors, and semiconductor memory device including the same 有权能够补偿晶体管之间的失配的位线读出放大器和包括其的半导体存储器件公开(公告)号：US09431071B2
公开(公告)日：2016-08-30
申请号：US14658353
申请日：2015-03-16
发明人： Jong-Ho Moon , Tai-Young Ko , Hyung-Sik You
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C7/12
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091
摘要： A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line.
摘要翻译： 位线读出放大器可以包括上拉驱动电路，下拉驱动电路和锁存型读出放大器。 上拉驱动电路包括连接在电源电压线和第一驱动电源线之间的多个PMOS晶体管，并且可以被配置为响应于上升控制在第一驱动电源线上提供第一驱动电流 信号。 下拉驱动电路可以被配置为响应于下降控制信号在第二驱动电源线上提供第二驱动电流。 闩锁型读出放大器可以连接在第一驱动电源线和第二驱动电源线之间，并且可以被配置为感测和放大位线和互补位线之间的电压差。
-
3.发明授权Bit-line sense amplifier, semiconductor memory device and memory system including the same 有权位线读出放大器，半导体存储器件和存储器系统都包括在内公开(公告)号：US09449670B2
公开(公告)日：2016-09-20
申请号：US13960617
申请日：2013-08-06
发明人： Hyung-Sik You , Jung-Bae Lee
IPC分类号： G11C11/40 , G11C11/402 , G11C11/406 , G11C11/4091
CPC分类号： G11C11/402 , G11C11/406 , G11C11/4091 , G11C2207/002 , G11C2211/4063 , G11C2211/4065
摘要： A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.
摘要翻译： 提供了一种半导体存储器件，其包括读出放大器，连接到第一存储器块的多个存储器单元的位线，连接到第二存储器块的多个存储器单元的互补位线，第一开关，被配置为 将位线连接到读出放大器，以及配置成将互补位线连接到读出放大器的第二开关。 第一开关被配置为当第二存储器块执行刷新操作时将位线与读出放大器电分离。
-
-
搜索结果
3 条记录 (耗时 0.015 秒)
