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公开(公告)号：US20220068859A1
公开(公告)日：2022-03-03
申请号：US17207242
申请日：2021-03-19
发明人： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC分类号： H01L23/00 , H01L27/108 , G11C11/408 , G11C11/4091 , H01L25/065 , H01L25/18
摘要： A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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公开(公告)号：US11410951B2
公开(公告)日：2022-08-09
申请号：US17207242
申请日：2021-03-19
发明人： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC分类号： H01L27/108 , G11C11/408 , H01L25/065 , G11C11/4091 , H01L23/00 , H01L25/18
摘要： A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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3.发明授权Bit-line sense amplifier capable of compensating mismatch between transistors, and semiconductor memory device including the same 有权能够补偿晶体管之间的失配的位线读出放大器和包括其的半导体存储器件公开(公告)号：US09431071B2
公开(公告)日：2016-08-30
申请号：US14658353
申请日：2015-03-16
发明人： Jong-Ho Moon , Tai-Young Ko , Hyung-Sik You
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C7/12
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091
摘要： A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line.
摘要翻译： 位线读出放大器可以包括上拉驱动电路，下拉驱动电路和锁存型读出放大器。 上拉驱动电路包括连接在电源电压线和第一驱动电源线之间的多个PMOS晶体管，并且可以被配置为响应于上升控制在第一驱动电源线上提供第一驱动电流 信号。 下拉驱动电路可以被配置为响应于下降控制信号在第二驱动电源线上提供第二驱动电流。 闩锁型读出放大器可以连接在第一驱动电源线和第二驱动电源线之间，并且可以被配置为感测和放大位线和互补位线之间的电压差。
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公开(公告)号：US20230180468A1
公开(公告)日：2023-06-08
申请号：US18052689
申请日：2022-11-04
发明人： Kiseok Lee , Moonyoung Jeong , Jong-Ho Moon , Han-Sik Yoo , Keunnam Kim , Hyungeun Choi
IPC分类号： H01L27/108 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00
CPC分类号： H01L27/10897 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L25/0657 , H01L27/10805 , H01L27/10894 , H01L2224/06515 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
摘要： A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.
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公开(公告)号：US11495284B2
公开(公告)日：2022-11-08
申请号：US17202466
申请日：2021-03-16
发明人： Jong-Ho Moon , Sung-Hwan Jang
IPC分类号： G11C7/12 , G11C11/4091 , G11C11/4074 , G11C11/4096 , G11C11/4094 , G11C11/4076
摘要： Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.
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公开(公告)号：US10784184B2
公开(公告)日：2020-09-22
申请号：US16263408
申请日：2019-01-31
发明人： Soojung Rho , Chisung Oh , Kyomin Sohn , Yong-Ki Kim , Jong-Ho Moon , SeungHan Woo , Jaeyoun Youn
IPC分类号： H01L23/48 , H01L23/538 , H01L23/528 , H01L23/522 , H01L25/065
摘要： A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.
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