公开(公告)号：US20210028286A1

公开(公告)日：2021-01-28

申请号：US16837408

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hokyun AN ,  Bumsoo KIM ,  Hyunseung KIM ,  Guangfan JIAO

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8238

Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

公开(公告)号：US20240162307A1

公开(公告)日：2024-05-16

申请号：US18392870

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hokyun AN ,  Bumsoo KIM ,  Hyunseung KIM ,  Guangfan JIAO

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

公开(公告)号：US20220093755A1

公开(公告)日：2022-03-24

申请号：US17544158

申请日：2021-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hokyun AN ,  Bumsoo KIM ,  Hyunseung KIM ,  Guangfan JIAO

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3115 ,  H01L27/092

Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.