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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250081513A1

    公开(公告)日：2025-03-06

    申请号：US18594049

    申请日：2024-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae-Eon BAE ,  Hokyun AN

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

    Abstract: A semiconductor device includes: a substrate including a first active pattern and a second active pattern which are spaced apart from each other; a first gate structure disposed on the first active pattern; a second gate structure disposed on the second active pattern; and a channel semiconductor pattern disposed between the second active pattern and the second gate structure, wherein the first gate structure includes: a first insulating pattern, a second insulating pattern and a first high-k dielectric pattern, which are stacked on the first active pattern, wherein the second gate structure includes: a third insulating pattern and a second high-k dielectric pattern, which are stacked on the channel semiconductor pattern, and wherein a thickness of the third insulating pattern ranges from 12 Å to 13 Å.

    SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210028286A1

    公开(公告)日：2021-01-28

    申请号：US16837408

    申请日：2020-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hokyun AN ,  Bumsoo KIM ,  Hyunseung KIM ,  Guangfan JIAO

    IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8238

    Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250048717A1

    公开(公告)日：2025-02-06

    申请号：US18745614

    申请日：2024-06-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hokyun AN ,  Kibum LEE ,  Jungmin CHO ,  Sunggyu CHOI

    IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324

    Abstract: A method of manufacturing a semiconductor device includes forming, on a substrate, a semiconductor material layer including germanium, forming a diffusion material layer in an upper portion of the substrate adjacent to the semiconductor material layer by performing a first heat treatment on the semiconductor material layer, removing the semiconductor material layer, recrystallizing the diffusion material layer by performing a second heat treatment on the diffusion material layer, and forming a fin-type structure by removing at least a portion of the substrate and at least a portion of the diffusion material layer. The diffusion material layer includes germanium diffused from the semiconductor material layer. A germanium concentration in the fin-type structure decreases from an upper surface of the fin-type structure toward a lower surface of the fin-type structure along a vertical direction perpendicular to a top surface of the substrate.

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220093755A1

    公开(公告)日：2022-03-24

    申请号：US17544158

    申请日：2021-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hokyun AN ,  Bumsoo KIM ,  Hyunseung KIM ,  Guangfan JIAO

    IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3115 ,  H01L27/092

    Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

    DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER
    6.
    发明申请
    DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER 有权

    公开(公告)号：US20220246620A1

    公开(公告)日：2022-08-04

    申请号：US17723218

    申请日：2022-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

    IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

    Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

    DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER
    7.
    发明申请
    DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER 有权

    公开(公告)号：US20210066304A1

    公开(公告)日：2021-03-04

    申请号：US16837274

    申请日：2020-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

    IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

    Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

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