公开(公告)号：US20180375023A1

公开(公告)日：2018-12-27

申请号：US15867951

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ji SONG ,  Sung-won KIM ,  II-mok PARK ,  Jong-chul PARK ,  Ji-hyun JEONG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/126 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.