公开(公告)号：US20180375023A1

公开(公告)日：2018-12-27

申请号：US15867951

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ji SONG ,  Sung-won KIM ,  II-mok PARK ,  Jong-chul PARK ,  Ji-hyun JEONG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/126 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.

公开(公告)号：US20190288038A1

公开(公告)日：2019-09-19

申请号：US16433511

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ji SONG ,  Jung-hoon PARK ,  Sung-ho EUN

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.