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    MEMORY DEVICES
    1.
    发明申请
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20200265874A1

    公开(公告)日：2020-08-20

    申请号：US16869804

    申请日：2020-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-hyun JEONG ,  Jae-hyun PARK

    IPC: G11C5/06 ,  H01L27/24 ,  G11C5/02 ,  G11C13/00 ,  H01L27/22

    Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200227481A1

    公开(公告)日：2020-07-16

    申请号：US16835667

    申请日：2020-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-hyun JEONG ,  Gwan-hyeob KOH ,  Dae-hwan KANG

    IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  G11C13/00

    Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

    MEMORY DEVICES
    4.
    发明申请
    MEMORY DEVICES 有权

    公开(公告)号：US20220076713A1

    公开(公告)日：2022-03-10

    申请号：US17526155

    申请日：2021-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-hyun JEONG ,  Jae-hyun PARK

    IPC: G11C5/06 ,  H01L27/24 ,  G11C5/02 ,  G11C13/00 ,  H01L27/22

    Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

    MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20180375023A1

    公开(公告)日：2018-12-27

    申请号：US15867951

    申请日：2018-01-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seul-ji SONG ,  Sung-won KIM ,  II-mok PARK ,  Jong-chul PARK ,  Ji-hyun JEONG

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/126 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.

    MEMORY DEVICES
    6.
    发明申请
    MEMORY DEVICES 有权

    公开(公告)号：US20210134332A1

    公开(公告)日：2021-05-06

    申请号：US17143340

    申请日：2021-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-hyun JEONG ,  Jae-hyun PARK

    IPC: G11C5/06 ,  H01L27/24 ,  G11C5/02 ,  G11C13/00 ,  H01L27/22

    Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

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