公开(公告)号：US20220416082A1

公开(公告)日：2022-12-29

申请号：US17585686

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUJIN JUNG ,  JINBUM KIM ,  DAHYE KIM ,  INGYU JANG ,  DONGSUK SHIN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

公开(公告)号：US20220352309A1

公开(公告)日：2022-11-03

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  DAHYE KIM ,  DONGMYOUNG KIM ,  DONGWOO KIM ,  YONGJUN NAM ,  SANGMOON LEE ,  INGYU JANG ,  SUJIN JUNG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.