公开(公告)号：US09391646B2

公开(公告)日：2016-07-12

申请号：US14224572

申请日：2014-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Iddo Naiss ,  Uri Beitler ,  Jun Jin Kong

IPC: G06F11/00 ,  H03M13/00 ,  H03M13/11 ,  G06F11/10

CPC classification number: H03M13/6312 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/152

Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

Abstract translation: 存储器控制器包括联合源通道编码器电路和联合源通道解码器电路。 联合源信道编码器电路源对接收到的数据进行编码，独立于接收到的数据是否是可压缩数据，对源编码数据执行纠错编码，并将源编码数据存储在存储器件中。 联合源信道解码器电路在读取数据的纠错编码的迭代之间对从存储器件读取的数据执行源解码，并将读取的数据输出到缓冲存储器和存储设备接口中的至少一个。 联合源信道解码器电路执行读取数据的源解码，与读数据是否为压缩数据无关。

公开(公告)号：US10262728B2

公开(公告)日：2019-04-16

申请号：US15288443

申请日：2016-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Iddo Naiss ,  Noam Livne ,  Elona Erez ,  Jun Jin Kong

IPC: G06F11/10 ,  G11C11/56 ,  G11C29/52 ,  G11C29/00

Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.