公开(公告)号：US20180144786A1

公开(公告)日：2018-05-24

申请号：US15812497

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young LIM ,  In-Su CHOI ,  Dimin NIU ,  In-Dong KIM

IPC: G11C11/4096 ,  G06F11/20 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.

公开(公告)号：US20140143478A1

公开(公告)日：2014-05-22

申请号：US14015536

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung SHIN ,  Sang-Joon HWANG ,  Seung-Man SHIN ,  In-Su CHOI ,  Jung-Ho JUNG

IPC: G06F12/02

CPC classification number: G06F12/06 ,  G06F2212/205 ,  G11C11/005 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Abstract translation: 半导体存储器件包括第一类型存储器的第一存储器块; 以及具有与第一类型不同类型的第二类型存储器的第二存储块。 第一存储块的第一地址区和第二存储块的第二地址区被包括在相同的地址域中。 第一和第二存储块中的每一个被包括地址域的地址的地址信号访问，而第二存储块是非易失性存储器。

公开(公告)号：US20140078846A1

公开(公告)日：2014-03-20

申请号：US13970738

申请日：2013-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung SHIN ,  Seung-Man SHIN ,  In-Su CHOI

IPC: G11C11/34

CPC classification number: G11C11/34 ,  G11C8/18 ,  G11C11/40615 ,  G11C11/40618

Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

Abstract translation: 半导体存储器件包括内部地址产生电路; 内部命令发生电路; 以及包括一个或多个存储体组的存储单元阵列。 半导体存储器件被配置为使得当读取命令或写入命令被输入时，如果存储器单元阵列的一个或多个存储体组中的第一存储体组的多个存储体的第一部分执行 读取操作或写入操作时，第一存储体组的多个存储体的第二部分执行刷新操作。