公开(公告)号：US20140143478A1

公开(公告)日：2014-05-22

申请号：US14015536

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung SHIN ,  Sang-Joon HWANG ,  Seung-Man SHIN ,  In-Su CHOI ,  Jung-Ho JUNG

IPC: G06F12/02

CPC classification number: G06F12/06 ,  G06F2212/205 ,  G11C11/005 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Abstract translation: 半导体存储器件包括第一类型存储器的第一存储器块; 以及具有与第一类型不同类型的第二类型存储器的第二存储块。 第一存储块的第一地址区和第二存储块的第二地址区被包括在相同的地址域中。 第一和第二存储块中的每一个被包括地址域的地址的地址信号访问，而第二存储块是非易失性存储器。

公开(公告)号：US20140078846A1

公开(公告)日：2014-03-20

申请号：US13970738

申请日：2013-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung SHIN ,  Seung-Man SHIN ,  In-Su CHOI

IPC: G11C11/34

CPC classification number: G11C11/34 ,  G11C8/18 ,  G11C11/40615 ,  G11C11/40618

Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

Abstract translation: 半导体存储器件包括内部地址产生电路; 内部命令发生电路; 以及包括一个或多个存储体组的存储单元阵列。 半导体存储器件被配置为使得当读取命令或写入命令被输入时，如果存储器单元阵列的一个或多个存储体组中的第一存储体组的多个存储体的第一部分执行 读取操作或写入操作时，第一存储体组的多个存储体的第二部分执行刷新操作。

公开(公告)号：US20210166740A1

公开(公告)日：2021-06-03

申请号：US17172328

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Sung SHIN ,  Ik-Joon CHOI ,  So-Young KIM ,  Tae-Kyu BYUN ,  Jae-Youn YOUN

IPC: G11C7/10 ,  G11C5/06 ,  G11C5/04 ,  G06F3/06 ,  G06F7/523 ,  G06F12/06 ,  G11C7/06 ,  G11C7/22

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

公开(公告)号：US20190258487A1

公开(公告)日：2019-08-22

申请号：US16199679

申请日：2018-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung SHIN ,  Sung-Ho PARK ,  Chan-Kyung KIM ,  Yong-Sik PARK ,  Sang-Hoon SHIN

IPC: G06F9/355 ,  G06F9/345 ,  G06F9/30

Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

公开(公告)号：US20190189221A1

公开(公告)日：2019-06-20

申请号：US16127793

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taek-Soo KIM ,  Chan-lk PARK ,  Hyun-Sung SHIN ,  Sang-Hoan CHANG

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C8/14 ,  G11C7/18 ,  G11C7/10 ,  G11C19/28 ,  G11C29/42 ,  G11C5/14

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.