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    METHOD OF REPAIRING A MEMORY DEVICE AND METHOD OF BOOTING A SYSTEM INCLUDING THE MEMORY DEVICE
    1.
    发明申请
    METHOD OF REPAIRING A MEMORY DEVICE AND METHOD OF BOOTING A SYSTEM INCLUDING THE MEMORY DEVICE 有权
    修复存储器件的方法和包括存储器件的系统的打包方法

    公开(公告)号：US20150131393A1

    公开(公告)日：2015-05-14

    申请号：US14534492

    申请日：2014-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min-Yeab CHOO ,  Bu-Il JUNG ,  Do-Geun KIM ,  Mi-Kyoung PARK ,  Dong-Yang LEE ,  Sun-Young LIM ,  Ju-Yun JUNG ,  Hyuk HAN

    IPC: G11C29/00 ,  G11C29/04

    CPC classification number: G11C29/04 ,  G11C29/78 ,  G11C29/785 ,  G11C29/88

    Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

    Abstract translation: 一种修复包括引导存储器区域，正常存储器区域和冗余存储器区域的存储器件的方法，所述冗余存储器区域包括多个修复存储器单元，包括通过执行以下操作中的至少一个修复引导存储器区域：排除第一 引导存储器区域的故障存储器单元用作存储，并且用修复存储器单元的引导修复存储器单元替换第一故障存储器单元，每个第一故障存储器单元具有至少一个故障存储器单元; 并且在修复引导存储器区域之后，通过执行排除第二故障存储器单元中的至少一个作为存储来修复正常存储器区域，并用修复存储器单元的正常修复存储器单元替换第二故障存储器单元。

    STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME
    2.
    发明申请
    STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME 审中-公开
    存储设备和包含该存储设备的存储系统

    公开(公告)号：US20150039814A1

    公开(公告)日：2015-02-05

    申请号：US14449343

    申请日：2014-08-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young LIM ,  Jin-Hwa LEE ,  Dong-Hwi KIM

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7201

    Abstract: A storage device may include a nonvolatile storage and a storage controller. The nonvolatile storage may include a map table which stores information including a logical address, a physical address corresponding to the logical address and a correlation index designating the physical address. The storage controller is configured to transmit the information to an external host device, and to access the nonvolatile storage based on a request and the correlation index, each of the request and the correlation index transmitted from the host device.

    Abstract translation: 存储设备可以包括非易失性存储器和存储控制器。 非易失性存储器可以包括映射表，其存储包括逻辑地址，对应于逻辑地址的物理地址和指定物理地址的相关指标的信息。 存储控制器被配置为将信息发送到外部主机设备，并且基于从主机设备发送的请求和相关索引，每个请求和相关索引，访问非易失性存储器。

    INTERFACE METHOD OF MEMORY SYSTEM, INTERFACE CIRCUITRY AND MEMORY MODULE
    3.
    发明申请
    INTERFACE METHOD OF MEMORY SYSTEM, INTERFACE CIRCUITRY AND MEMORY MODULE 审中-公开

    公开(公告)号：US20180144786A1

    公开(公告)日：2018-05-24

    申请号：US15812497

    申请日：2017-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young LIM ,  In-Su CHOI ,  Dimin NIU ,  In-Dong KIM

    IPC: G11C11/4096 ,  G06F11/20 ,  G06F11/10 ,  G11C29/52

    Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.

    METHOD OF OPERATING MEMORY SYSTEM
    5.
    发明申请
    METHOD OF OPERATING MEMORY SYSTEM 审中-公开
    操作记忆系统的方法

    公开(公告)号：US20150128000A1

    公开(公告)日：2015-05-07

    申请号：US14531250

    申请日：2014-11-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Yun JUNG ,  Min-Yeab CHOO ,  Do-Geun KIM ,  Mi-Kyoung PARK ,  Dong-Yang LEE ,  Sun-Young LIM ,  Bu-Il JUNG ,  Hyuk HAN

    IPC: G11C29/44 ,  G06F11/22

    CPC classification number: G06F11/2268 ,  G11C16/20 ,  G11C2029/4402

    Abstract: In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system.

    Abstract translation: 在操作包括存储器设备和存储器控制器的存储器系统的方法中，存储器控制器从包括在存储器件中的故障信息区域读取故障信息。 存储器控制器基于故障信息将与程序相关的逻辑地址映射到安全区域的物理地址，以将程序存储在除了故障信息区域以外的安全区域和包括在存储器件中的故障区域。 存储器控制器根据地址映射将程序加载到存储器件的安全区域。 根据示例性实施例的操作存储器系统的方法增加了存储器系统的性能。

    MEMORY MODULE, OPERATION METHOD THEROF, AND OPERATION METHOD OF HOST
    7.
    发明申请
    MEMORY MODULE, OPERATION METHOD THEROF, AND OPERATION METHOD OF HOST 审中-公开

    公开(公告)号：US20190236030A1

    公开(公告)日：2019-08-01

    申请号：US16103058

    申请日：2018-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young LIM ,  Dimin NIU ,  Jae-Gon LEE

    IPC: G06F12/14 ,  G06F3/06 ,  G06F21/79

    CPC classification number: G06F12/1433 ,  G06F3/0622 ,  G06F3/0679 ,  G06F21/79

    Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.

    MEMORY SYSTEM AND ELECTRONIC DEVICE
    10.
    发明申请
    MEMORY SYSTEM AND ELECTRONIC DEVICE 有权
    存储系统和电子设备

    公开(公告)号：US20150363106A1

    公开(公告)日：2015-12-17

    申请号：US14722158

    申请日：2015-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sun-Young LIM ,  Dong-Yang LEE ,  Young-Jin CHO ,  Oh-Seong KWON

    IPC: G06F3/06

    CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

    Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

    Abstract translation: 电子设备包括存储器控制器; 耦合到所述存储器控制器的第一存储器件; 耦合到所述存储器控制器的第二存储器设备，所述第二存储器设备是与所述第一存储器设备不同类型的存储器; 以及存储器控制器和第二存储器件之间的转换电路。 存储器控制器被配置为根据第一定时方案向第一存储器设备发送第一命令和第一数据以访问第一存储器件，并且根据第一定时方案向转换电路发送第二命令和数据包到第 访问第二个存储设备。 转换电路被配置为接收第二命令和分组，并且基于第二命令和分组访问第二存储器设备。

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