公开(公告)号：US20240071983A1

公开(公告)日：2024-02-29

申请号：US18227697

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongken YU ,  Cheolsoo HAN ,  Kwangjin BAE ,  Youngjin JANG ,  Inwook JUNG ,  Minchul CHO

IPC: H01L23/00 ,  B23K3/06

CPC classification number: H01L24/75 ,  B23K3/0623 ,  H01L2224/75804

Abstract: A solder ball attaching apparatus includes a working die, having an internal space maintained in a vacuum state, and a plurality of lifting members installed on the working die to be movable upwardly and downwardly. The working die may be provided with an upper plate on which the lifting members are installed. The upper plate may be provided with an insertion groove, into which an upper end portion of the lifting member is inserted when the lifting member is lowered, and a locking groove into which a lower end portion of the lifting member is inserted when the lifting member is raised. The lifting member may be lowered by a chip when the chip is seated on the lifting member and may be raised by elastic restoring force when the chip is removed.

公开(公告)号：US20220020656A1

公开(公告)日：2022-01-20

申请号：US17185116

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon JUNG ,  Young Lyong KIM ,  Cheolsoo HAN

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

公开(公告)号：US20240023346A1

公开(公告)日：2024-01-18

申请号：US18166322

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghun CHEONG ,  Minchul CHO ,  Cheolsoo HAN

IPC: H10B80/00 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L24/45 ,  H01L24/48 ,  H01L24/32 ,  H01L24/33 ,  H01L23/564 ,  H01L24/83 ,  H01L24/85 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45147 ,  H01L2224/45124 ,  H01L2224/45184 ,  H01L2224/45155 ,  H01L2224/4518 ,  H01L2224/45144 ,  H01L2224/45139 ,  H01L2224/45171 ,  H01L2224/45111 ,  H01L2224/45166 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83007 ,  H01L2224/85007 ,  H01L2224/92147

Abstract: A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

公开(公告)号：US20230178518A1

公开(公告)日：2023-06-08

申请号：US17889053

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung DO ,  Seunghyun GO ,  Jungsik LEE ,  Jongho LEE ,  Younghun CHEONG ,  Cheolsoo HAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/4911 ,  H01L2224/49421 ,  H01L2224/49422 ,  H01L2224/49426 ,  H01L2225/06562 ,  H01L2224/49052 ,  H01L2224/48091 ,  H01L2224/05624 ,  H01L24/05 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85484 ,  H01L2224/85466 ,  H01L24/85 ,  H01L2224/45144 ,  H01L24/45

Abstract: A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.