公开(公告)号：US09923529B2

公开(公告)日：2018-03-20

申请号：US15137349

申请日：2016-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siddharth Seth ,  Venumadhav Bhagavatula ,  Ivan Lu ,  Sang Won Son

IPC: H04W72/04 ,  H03F3/24 ,  H03F3/19 ,  H04L5/22 ,  H04B1/04 ,  H04W72/12

CPC classification number: H03F3/245 ,  H03F3/19 ,  H03F3/217 ,  H03F3/24 ,  H03F2200/451 ,  H04B1/0475 ,  H04B2001/0408 ,  H04L5/22 ,  H04W72/1263

Abstract: Apparatuses, systems, and methods for a digital power amplifier (DPA) to generate a monotonic and linear ramp-up and ramp-down for a time division multiple access (TDMA) slot transmission are described. In one aspect, a monotonic and linear amplitude-to-control input code relationship model is generated for the DPA and stored. When the DPA needs to generate a ramp-up or ramp-down, the stored monotonic and linear amplitude-to-control input code relationship model is used to shape the input control code before it is input into the DPA. A new monotonic and linear amplitude-to-control input code relationship model may be generated and stored if the operating conditions change. The apparatuses, systems, and methods described herein may be applied to a multi-standard broadband modem chip capable of 2G transmission.