公开(公告)号：US20220028834A1

公开(公告)日：2022-01-27

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JINKYEONG SEOL ,  SANGHOON LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

公开(公告)号：US20250029942A1

公开(公告)日：2025-01-23

申请号：US18596286

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raeyoung KANG ,  MINKI KIM ,  JIHOON KIM ,  JINKYEONG SEOL

IPC: H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a lower structure and an upper structure on the lower structure. The lower structure includes a first substrate, a first through-electrode penetrating the first substrate in a first direction, a first pad connected to the first through-electrode, and a first protective layer surrounding the first pad. The upper structure includes a second substrate, a second through-electrode penetrating the second substrate in the first direction, a second pad connected to the second through-electrode, and a second protective layer surrounding the second pad. The second pad is offset from the first pad in a second direction crossing the first direction. The first pad has a first portion not overlapping the second pad. A first barrier pattern is disposed between the first portion and the second protective layer. A portion of the first barrier pattern is disposed between the first pad and the second pad.

公开(公告)号：US20240404970A1

公开(公告)日：2024-12-05

申请号：US18441578

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINKI KIM ,  RAEYOUNG KANG ,  JIHOON KIM ,  JINKYEONG SEOL ,  HYUEKJAE LEE

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.