公开(公告)号：US20240404970A1

公开(公告)日：2024-12-05

申请号：US18441578

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINKI KIM ,  RAEYOUNG KANG ,  JIHOON KIM ,  JINKYEONG SEOL ,  HYUEKJAE LEE

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.

公开(公告)号：US20240332255A1

公开(公告)日：2024-10-03

申请号：US18742838

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20220157779A1

公开(公告)日：2022-05-19

申请号：US17367005

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD,

Inventor： JIHOON KIM

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.

公开(公告)号：US20240088105A1

公开(公告)日：2024-03-14

申请号：US18518591

申请日：2023-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIHOON KIM

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L2225/06517

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.

公开(公告)号：US20250029942A1

公开(公告)日：2025-01-23

申请号：US18596286

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raeyoung KANG ,  MINKI KIM ,  JIHOON KIM ,  JINKYEONG SEOL

IPC: H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a lower structure and an upper structure on the lower structure. The lower structure includes a first substrate, a first through-electrode penetrating the first substrate in a first direction, a first pad connected to the first through-electrode, and a first protective layer surrounding the first pad. The upper structure includes a second substrate, a second through-electrode penetrating the second substrate in the first direction, a second pad connected to the second through-electrode, and a second protective layer surrounding the second pad. The second pad is offset from the first pad in a second direction crossing the first direction. The first pad has a first portion not overlapping the second pad. A first barrier pattern is disposed between the first portion and the second protective layer. A portion of the first barrier pattern is disposed between the first pad and the second pad.

公开(公告)号：US20210028146A1

公开(公告)日：2021-01-28

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240120299A1

公开(公告)日：2024-04-11

申请号：US18234609

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIHOON KIM

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0657 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2225/06565

Abstract: A semiconductor package includes a first semiconductor structure including a first semiconductor substrate and a lower through structure that penetrates the first semiconductor substrate, a connection structure on the first semiconductor structure and a second semiconductor structure on the connection structure, the second semiconductor structure including a second semiconductor substrate and an upper through structure that penetrates the second semiconductor substrate, where the connection structure includes a lower curved pad on the lower through structure, and an upper curved pad on the lower curved pad, where a top surface of the lower curved pad includes a curved surface, where a bottom surface of the upper curved pad includes a curved surface, and where the upper curved pad is connected to the upper through structure.

公开(公告)号：US20230253363A1

公开(公告)日：2023-08-10

申请号：US18133959

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/80 ,  H01L25/18 ,  H01L24/08 ,  H01L21/565 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20230094436A1

公开(公告)日：2023-03-30

申请号：US17706137

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHWAN LIM ,  WALTER JUN ,  JAEEUN KIM ,  JIHOON KIM ,  KIHYEON MYUNG ,  HYUNJUNG YOO ,  JUNGWOO LEE

IPC: G06F3/06 ,  G06F13/42

Abstract: A system includes a transmission device and a reception device that are connected through a link. The reception device includes a reception buffer configured to receive and store transaction layer packets and a reception flow controller configured to generate flow control packets by monitoring an occupation state of the reception buffer. The transmission device includes a transmission buffer, a transmission flow controller and a dynamic frequency controller. The transmission buffer stores pending transaction layer packets to be transferred to the reception device. The transmission flow controller controls a flow of transaction layer packets to be transferred to the reception device based on the flow control packets received from the reception device. The dynamic frequency controller controls a frequency of an internal clock signal of the transmission device by monitoring a state of the transmission buffer and a state of the transmission flow controller.