公开(公告)号：US11978696B2

公开(公告)日：2024-05-07

申请号：US17568465

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyujin Choi ,  Jae-Ean Lee ,  Changeun Joo

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/08 ,  H01L25/105 ,  H01L2224/0603 ,  H01L2224/08235

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

公开(公告)号：US20240387486A1

公开(公告)日：2024-11-21

申请号：US18584905

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahee Kim ,  Hongwon Kim ,  Jae-Ean Lee ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: An example semiconductor package includes a substrate, a first semiconductor chip mounted on the substrate, a mold layer on the substrate to cover the first semiconductor chip, and outer terminals positioned below the substrate. The substrate includes a first interconnection layer, a second interconnection layer on the first interconnection layer, a passive device mounted on a bottom surface of the second interconnection layer, and a connection member at a side of the passive device and between the first interconnection layer and the second interconnection layer to connect the first interconnection layer to the second interconnection layer. The outer terminals are coupled to a bottom surface of the first interconnection layer, the passive device includes a first pad on a top surface of the passive device, and an interconnection pattern of the second interconnection layer contacts the first pad.

公开(公告)号：US20240404936A1

公开(公告)日：2024-12-05

申请号：US18417921

申请日：2024-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyujin Choi ,  Dahee Kim ,  Jae-Ean Lee ,  Taehoon Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065

Abstract: A stacked structure includes a lower substrate and a first semiconductor chip stacked on an upper surface of the lower substrate, the lower substrate includes a lower conductor pattern disposed on the upper surface of the lower substrate, the first semiconductor chip may have first and second surfaces facing each other, the second surface of the first semiconductor chip may face the upper surface of the lower substrate, and the first semiconductor chip may include a first conductor pattern disposed on the second surface. The first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, and the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction.

公开(公告)号：US20220384324A1

公开(公告)日：2022-12-01

申请号：US17568465

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyujin Choi ,  Jae-Ean Lee ,  Changeun Joo

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.