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公开(公告)号：US20200379541A1
公开(公告)日：2020-12-03
申请号：US16994894
申请日：2020-08-17
发明人： SEOK-JU YOON , Nak-Woo Sung , Seung-Chull Suh , Taek-ki Kim , Jae-Joon Yoo , Eun-Ok Jo
IPC分类号： G06F1/329 , G06F1/3296 , G06F1/3228 , G06F1/324
摘要： A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.
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公开(公告)号：US11656675B2
公开(公告)日：2023-05-23
申请号：US17739732
申请日：2022-05-09
发明人： Seok-Ju Yoon , Nak-Woo Sung , Seung-Chull Suh , Taek-Ki Kim , Jae-Joon Yoo , Eun-Ok Jo
IPC分类号： G06F1/329 , G06F1/3228 , G06F1/324 , G06F1/3296 , G06F15/167 , G06F9/50
CPC分类号： G06F1/329 , G06F1/324 , G06F1/3228 , G06F1/3296
摘要： A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.
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公开(公告)号：US09774939B2
公开(公告)日：2017-09-26
申请号：US15161754
申请日：2016-05-23
发明人： Min-Young Park , Kwangmin Kil , Jae-Joon Yoo , Chang-Youl Lee , Janghoon Kang , Taeeon Kim , Youngbae Park
CPC分类号： H04R1/028 , H04M1/03 , H04R1/023 , H04R1/025 , H04R2499/11
摘要： A slim electronic device is provided. The slim electronic device includes a substrate having an opening formed therein, and an audio component accommodated in the opening of the substrate without overlapping the substrate and disposed such that the top and bottom thereof are substantially parallel to the top and bottom of the substrate.
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公开(公告)号：US11327555B2
公开(公告)日：2022-05-10
申请号：US16994894
申请日：2020-08-17
发明人： Seok-Ju Yoon , Nak-Woo Sung , Seung-Chull Suh , Taek-Ki Kim , Jae-Joon Yoo , Eun-Ok Jo
IPC分类号： G06F1/329 , G06F1/3228 , G06F1/324 , G06F1/3296 , G06F15/167 , G06F9/50
摘要： A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.
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公开(公告)号：US10747297B2
公开(公告)日：2020-08-18
申请号：US15797383
申请日：2017-10-30
发明人： Seok-Ju Yoon , Nak-Woo Sung , Seung-Chull Suh , Taek-Ki Kim , Jae-Joon Yoo , Eun-Ok Jo
IPC分类号： G06F1/329 , G06F1/324 , G06F1/3228 , G06F15/167 , G06F1/3296
摘要： A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.
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公开(公告)号：US09338930B2
公开(公告)日：2016-05-10
申请号：US14260708
申请日：2014-04-24
发明人： Won-Jea Jang , Dong-In Ha , Jin-Young Kwak , Gi-Heung Kim , Jung-Yoon Seo , Jae-Joon Yoo , Byoung-Hee Lee , Sung-Jin Choi
IPC分类号： H05K9/00
CPC分类号： H05K9/0035 , H05K9/0028
摘要： A shield reinforcing apparatus is provided. The shield reinforcing apparatus includes a printed circuit board, a shield member that covers the printed circuit board, and at least one shield reinforcing part provided in the printed circuit board and configured to contact the shield member to be pressed.
摘要翻译： 提供了屏蔽加强装置。 屏蔽增强装置包括印刷电路板，覆盖印刷电路板的屏蔽构件和设置在印刷电路板中并被配置为接触要被按压的屏蔽构件的至少一个屏蔽加强部。
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