公开(公告)号：US20180294219A1

公开(公告)日：2018-10-11

申请号：US15909212

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L23/528 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78 ,  H01L2027/11875

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10672442B2

公开(公告)日：2020-06-02

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419 ,  G11C11/418

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US20190080736A1

公开(公告)日：2019-03-14

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C11/418 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US20200168542A1

公开(公告)日：2020-05-28

申请号：US16774082

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L27/118 ,  H01L27/088

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10580733B2

公开(公告)日：2020-03-03

申请号：US15909212

申请日：2018-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10431272B2

公开(公告)日：2019-10-01

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US11437315B2

公开(公告)日：2022-09-06

申请号：US16774082

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US20190385653A1

公开(公告)日：2019-12-19

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Siddharth Gupta ,  ln-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.