公开(公告)号：US11042294B2

公开(公告)日：2021-06-22

申请号：US16730284

申请日：2019-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Choi ,  Young-jin Kim ,  Tae-soo Kim ,  Kang-tae Kim ,  Tae-hyung Kim

IPC: G06F3/0488 ,  G06F3/0481 ,  G06F3/0484

Abstract: A method of displaying for allowing a plurality of application windows to be easily controlled and a display device therefor are provided. A method of displaying a screen on a display device includes displaying a button on a touch screen; splitting the touch screen into a plurality of regions based on the position at which the button is displayed, receiving a touch input to move a displayed button, obtaining a slope value of a line connecting a start point of the touch input to an end point thereof, selecting a region corresponding to the slope value from among the plurality of regions split, and moving the button to a certain position included in a selected region.

公开(公告)号：US10978384B2

公开(公告)日：2021-04-13

申请号：US16519725

申请日：2019-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim ,  Chan-Ho Lee

IPC: H01L23/522 ,  G11C5/06 ,  H01L25/065 ,  G11C5/02 ,  G02B6/43

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

公开(公告)号：US09236870B2

公开(公告)日：2016-01-12

申请号：US14082308

申请日：2013-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim

IPC: G11C8/18 ,  H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406

CPC classification number: H03L7/0812 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/40611

Abstract: In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal. A path selection circuit is configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information.

Abstract translation: 在集成电路中，第一延迟锁定环电路被配置为基于相位调整的第一时钟信号来调整输入到第一时钟输入端的第一时钟信号的相位和至少一个发送和接收信息。 第二延迟锁定环电路被配置为基于相位调整的第二时钟信号来调整输入到第二时钟输入端的第二时钟信号的相位和至少一个发送和接收信息。 路径选择电路被配置为响应于选择信号选择通过第一延迟锁定环电路的第一信号路径和通过第二延迟锁定环电路的第二信号路径中的一个作为用于以下的至少一个的信号路径： 发送和接收信息。

公开(公告)号：US11437315B2

公开(公告)日：2022-09-06

申请号：US16774082

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US20190385653A1

公开(公告)日：2019-12-19

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Siddharth Gupta ,  ln-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US09660163B2

公开(公告)日：2017-05-23

申请号：US14736217

申请日：2015-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-in Yang ,  Tae-hyung Kim ,  Si-hyuk Lee ,  Sang-yeob Song ,  Cheol-soo Sone ,  Hak-hwan Kim ,  Jin-hyun Lee

IPC: H01L33/00 ,  H01L33/62 ,  H01L33/38 ,  H01L33/40 ,  H01L33/32 ,  H01L33/20 ,  H01L33/44

CPC classification number: H01L33/62 ,  H01L33/0025 ,  H01L33/005 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/32 ,  H01L33/382 ,  H01L33/387 ,  H01L33/405 ,  H01L33/44 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer.

公开(公告)号：US11646261B2

公开(公告)日：2023-05-09

申请号：US17197280

申请日：2021-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim ,  Chan-Ho Lee

IPC: H01L23/522 ,  H01L25/065 ,  G11C5/02 ,  H01L23/528 ,  G02B6/43

CPC classification number: H01L23/5222 ,  G11C5/02 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  G02B6/43

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

公开(公告)号：US10672442B2

公开(公告)日：2020-06-02

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419 ,  G11C11/418

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US20200075478A1

公开(公告)日：2020-03-05

申请号：US16519725

申请日：2019-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim ,  Chan-Ho Lee

IPC: H01L23/522 ,  G11C5/06 ,  G11C5/02 ,  H01L25/065

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

公开(公告)号：US20190080736A1

公开(公告)日：2019-03-14

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C11/418 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.