公开(公告)号：US20230180477A1

公开(公告)日：2023-06-08

申请号：US18161331

申请日：2023-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun YANG ,  Bio KIM ,  Yujin KIM ,  Kyong-won AN ,  Sookyeom YONG ,  Junggeun LEE ,  Youngjun CHEON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US20200091186A1

公开(公告)日：2020-03-19

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun YANG ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.