公开(公告)号：US11569261B2

公开(公告)日：2023-01-31

申请号：US17005495

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US10797074B2

公开(公告)日：2020-10-06

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US09276132B2

公开(公告)日：2016-03-01

申请号：US13969912

申请日：2013-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Sung Lee ,  Kyong-Won An

IPC: H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A nonvolatile memory device includes an insulating pattern extending in a first direction, a conductive pattern on the insulating pattern, and an electrode structure extending in the first direction. The electrode structure is adjacent the insulating pattern and conductive pattern, and includes an alternating pattern of gate electrodes and interlayer insulating films. A protection film adjacent a side surface of the electrode structure has a shorter length in the first direction than a length of the electrode structure.

Abstract translation: 非易失性存储器件包括沿第一方向延伸的绝缘图案，绝缘图案上的导电图案和沿第一方向延伸的电极结构。 电极结构与绝缘图案和导电图案相邻，并且包括栅电极和层间绝缘膜的交替图案。 与电极结构的侧表面相邻的保护膜在第一方向上比电极结构的长度具有更短的长度。

公开(公告)号：US20200091186A1

公开(公告)日：2020-03-19

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun YANG ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US09601496B2

公开(公告)日：2017-03-21

申请号：US14109159

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Lee ,  Hyunyong Go ,  Sunggil Kim ,  Kyong-Won An ,  Woosung Lee ,  Yongseok Cho

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/10855 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.