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公开(公告)号:US20220328511A1
公开(公告)日:2022-10-13
申请号:US17541444
申请日:2021-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Giyong CHUNG , Jae-Bok BAEK , Jaeryong SIM , Jeehoon HAN
IPC: H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582
Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.
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公开(公告)号:US20220310639A1
公开(公告)日:2022-09-29
申请号:US17656088
申请日:2022-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: GIYONG CHUNG , Seungyoon KIM , Jaeryong SIM , Jeehoon HAN
IPC: H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L25/065 , H01L23/528
Abstract: A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.
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公开(公告)号:US20210098483A1
公开(公告)日:2021-04-01
申请号:US16890500
申请日:2020-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seogoo KANG , Daehyun JANG , Jaeryong SIM , Jongseon AHN , Jeehoon HAN
IPC: H01L27/11575 , H01L27/11582 , H01L27/11556 , H01L27/11548
Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.
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公开(公告)号:US20220406801A1
公开(公告)日:2022-12-22
申请号:US17692797
申请日:2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seungyoon KIM , Jaeryong SIM , Jeehoon HAN
IPC: H01L27/11524 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L23/528 , H01L23/522
Abstract: A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.
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公开(公告)号:US20220102369A1
公开(公告)日:2022-03-31
申请号:US17318306
申请日:2021-05-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Giyong CHUNG , Jaeryong SIM , Kwangyoung JUNG , Jeehoon HAN
IPC: H01L27/11575 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11548 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.
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公开(公告)号:US20250056808A1
公开(公告)日:2025-02-13
申请号:US18931606
申请日:2024-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Giyong CHUNG , Jaeryong SIM , Kwangyoung JUNG , Jeehoon HAN
Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.
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公开(公告)号:US20210013304A1
公开(公告)日:2021-01-14
申请号:US16701427
申请日:2019-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyojoon RYU , Kiyoon KANG , Seogoo KANG , Shinhwan KANG , Jesuk MOON , Byunggon PARK , Jaeryong SIM , Jinsoo LIM , Jisung CHEON , Jeehoon HAN
IPC: H01L29/06 , H01L23/31 , G11C5/06 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.
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