公开(公告)号：US20240071921A1

公开(公告)日：2024-02-29

申请号：US18142795

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyu CHUNG ,  Sangjae LEE ,  Seungyoon KIM ,  Jaehwang SIM

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a first structure, a second structure on the first structure, and gate contact plugs penetrating through the first and second structures. The first structure may include a first stack structure including first gate layers and first insulating layers alternately stacked, a first pad capping pattern penetrating through at least a first portion of the first stack structure, and a first buffer capping pattern penetrating through at least a second portion of the first stack structure and spaced apart from the first pad capping pattern. The second structure may include a second stack structure including second gate layers and second insulating layers alternately stacked, and a second pad capping pattern penetrating through at least a portion of the second stack structure. The first gate layers may include first gate pads covered by the first pad capping pattern.

公开(公告)号：US20230054445A1

公开(公告)日：2023-02-23

申请号：US17739845

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Seungyoon KIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a stack structure of alternating interlayer insulating layers and gate electrodes, a separation structure vertically penetrating the stack structure and extending in a first direction, to separate the gate electrodes in a second direction, and vertical structures vertically penetrating the stack structure and arranged at a constant pitch. The vertical structures are arranged along array lines sequentially arranged in the second direction away from a side of the separation structure in a plan view. The vertical structures include a channel structure including a channel layer, a contact structure including a metal plug having an upper surface on a level higher than that of an upper surface of the channel structure, and a dummy structure disposed adjacent to the contact structure. The channel structure, the dummy structure, and the contact structure are disposed to be aligned with each other on at least one of the array lines.

公开(公告)号：US20220310639A1

公开(公告)日：2022-09-29

申请号：US17656088

申请日：2022-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： GIYONG CHUNG ,  Seungyoon KIM ,  Jaeryong SIM ,  Jeehoon HAN

IPC: H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/528

Abstract: A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.

公开(公告)号：US20240276719A1

公开(公告)日：2024-08-15

申请号：US18379849

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heesuk KIM ,  Seungyoon KIM ,  Yejin PARK ,  Inhwan BAEK ,  Jongseon AHN

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes: a lower circuit pattern disposed on a substrate; a common source plate (CSP) disposed on the lower circuit pattern; a channel connection pattern disposed on the CSP; a sacrificial layer structure disposed on the CSP and spaced apart from the channel connection pattern; a support layer disposed on the channel connection pattern and the sacrificial layer structure; first and second gate electrode structures including gate electrodes stacked on the support layer and spaced apart from each other; a first channel disposed on the CSP, wherein the first channel extends through the first gate electrode structure, the support layer and the channel connection pattern; and a contact plug extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern.

公开(公告)号：US20220406801A1

公开(公告)日：2022-12-22

申请号：US17692797

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon KIM ,  Jaeryong SIM ,  Jeehoon HAN

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.

公开(公告)号：US20220336421A1

公开(公告)日：2022-10-20

申请号：US17582387

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon KIM ,  Junghoon JUN ,  Sanghun CHUN ,  Jeehoon HAN

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.